A InGaP/GaAs HBT WLAN Power Amplifierwith Power Detector
...tors in series with each emitter or base as shown in Fig 1. (a) [6]. But a major problem with this ballast resistance is RF gain degrading. To solve the problem, the power transistor is designed with split FUC ballasting. Fig.1 (b) illustrates the scheme of the split FUC ballasting. The DC ballast resistors have no effect on RF gain performance. This structure shows improvement of about 2.5dB unilateral gain compared with base and emitter ballasting in 2.45GHz at same bias condition as shown in Fig 1. (c). Power transistor is modeled including self-heating and ambient temperature effects [7]. 111.2-STAGE POWER AMPLIFIER WITH POWER DETECTOR The topology of the power amplifier with proposed power detector is described in Fig. 2. A. Power detector So far, power detection by diode and log amp at power stage output is a simple method that detects power delivered to the load [8]. However, these detection methods decrease output power, directly. The output power is related to emitter area of power stage. To get same output power, the power transistor needs the more emitter area. The power detection at the input of the power stage is good approach to decrease output power loss. Because input power of power stage does not follow power stage output characteristics, the detection amplifier is needed to follow power stage output. A similar stmcture is seen by [9]. A part of detection is integrated in [9], which needs additional circuits to get power detector voltage. Also, it uses common bias circuit with power stage, power detector is always turned on. Considering detector transistor operation current in detection circuit, detector odoff is needed for not working detection. In this paper, a simple structure is integrated which get power detector voltage and tum odoff the power detection. As shown in Fig 3., because the detector amplifier of power detection is designed to follow power stage characteristics, it has some PAE degradation. To get less degradation, the detector amplifier is working in low bias region. It makes input of diode decreased, output detector voltage has low dynamic range. To compensate this effect, diode has V D m .~In ~mea~sur ement result, detector voltage of power detector has 0.2 to 1.2V as output power sweep 0 to 24". Fig. 3. power amplifier with power detector. Schematic diagram of the fabrication InGaPiGaAs 1 .z I 4.0 I g 0.6 01 L 0 5 10 15 20 outyut Powetldem] Fig. 4. Measured detector voltage A 25 E. Power ampliper The two-stage power amplifier was implemented with InGaPiGaAs HBT technology. The emitter sizes of the first stage and second stage HBT were 480um2 and 1920Um2. The detail schematic diagram of the circuit is displayed in Fig. 3. The power amplifier has an integrated input and interstage-matching network. The optimum input and output impedance of the HBTs are determined by large-signal models [7]. Bias circuits are completely on-chip except the collector circuitry of the output stage. This pari is off-chip to minimize power loss. The bias current level can be tuned to a desired value by controlling the reference voltage (Vref) in the bias circuit. IV. MEASUREMENT Fig. 5. is photograph of the power amplifier with integrated power detector. The chip size is 1.2mmx I.0mm. Fig. 6, 7, 8 shows the measured results of the power amplifier at 2.45GHz. The bias current is set to 37mA and 83mA for driver and power stage with a supply voltage of 3.3V Plds of 26 dBm and a gain 22 dB. The power added efficiency is over 31%. PIds is not degraded, as was expected. The gain is degraded ahout IdB.IMD is measured as -2OdBc at 24dBm in ?5oofaz offset frequency. In simulation result the IMD is -27dBc at 24dBm, the difference is presented by in accurate measu...